The present invention relates generally to validating the design of a processor, and particularly to validating the performance and functionality of a processor by using both high level and low level simulators of the processor design.
Typically, such validation requires booting one or more operating systems and running lengthy benchmark or validation programs on a low level simulator, hardware or software model, of the processor. The results of these runs can then provide information as to (1) the correct operation, the functionality, of the processor as well as (2) the performance of the processor. FIG. 1A is a block diagram of a prior art processor validation system 100 using only a low level simulator 110.
Low Level Simulators
Various types of low level simulators are used in validating the design of a processor. One type of low level simulator is the register transfer level (RTL) model of the processor. The RTL model is a one hundred percent accurate representation of a processor and is the same model used to design the processor. The RTL model of a processor is often expressed as a VHDL model of the processor. The VHDL model of a processor simulates each logic element in the processor and is a highly accurate representation of the processor. Alternatively, the RTL model of a processor is often expressed as a Verilog model of the processor. Verilog is a type of hardware description language (HDL) and is a textual way to describe a processor. The Verilog model of a processor is also a highly accurate representation of the processor.
These low level simulators simulate in software each logic element and the connections between these logic elements of a processor. In addition, a RTL model, a VHDL model, or a Verilog model of a processor is the same model used to represent the design of the processor. Consequently, executing operating system bootup programs and executing long-running benchmark or validation programs on such low level simulators ensures that the performance indicated by the model is highly accurate and also validates the actual hardware design by running pieces of code on the low level simulator of the hardware design.
However, executing operating system bootup programs and such long-running benchmark programs on low level simulators is usually infeasible in practice since simulation of these programs on such a software model is very slow. Low level simulators typically run at a speed of tens or hundreds of hertz. For example, it would take twenty-five years to simulate some of the longer running benchmark programs on the RTL model of a typical processor. Also, in validating the functionality and/or performance of a two hundred megahertz processor, a low level simulator running at a speed of one hundred hertz would require two million minutes, or about 3.8 years, to run an operating system bootup program, which the real processor would require only one minute to execute.
Another type of low level simulator is a hardware emulator configured with the design of the processor. One type of hardware emulator is a set of field programmable gate arrays (FPGAs), which, when configured with the design of the processor, would map each logical element of the processor into reconfigured hardware of the FPGAs. Consequently, such a hardware emulator is much faster than the RTL, VHDL, or Verilog models of a processor. Typically, a hardware emulator runs at a speed in the tens of kilohertz. Therefore, in validating the functionality and/or performance of the aforementioned two hundred megahertz processor, a low level hardware emulator running at a speed of ten kilohertz would require twenty thousand minutes, or about 13.9 days, to run an operating system bootup program, which the processor would require only one minute to execute.
However, a typical hardware emulator, such as a Quickturn emulator, is very expensive and costs millions of dollars. In addition, such an emulator typically requires about twenty-four hours to compile a program and is difficult to use.
High Level Simulators
Faster types of simulators, high level simulators, may be used to evaluate (1) the functionality and (2) the performance of a processor. FIG. 1B is a block diagram of another prior art processor validation system 150, which includes a first high level simulator 160, a trace file sampler 170, and a second high level simulator 180. FIG. 1B is a simplified representation of the prior art processor validation system described in U.S. Pat. No. 5,615,357. In this system, the first high level simulator is an instruction accurate simulator (IAS), while the second high level simulator is a cycle accurate simulator (CAS).
A high level simulator of a processor is a functional representation of the processor. A high level simulator does not simulate each gate of a processor and does not simulate each connection of the processor. Two types of high level simulators are the IAS of a processor and the CAS of a processor.
An instruction accurate simulator (IAS) of a processor models the processor at a much higher level of abstraction than low level simulators. Typically, an IAS of a processor runs at speeds from one megahertz to one hundred megahertz. The IAS of a processor models processor functionality at an abstract level but does not model details of the processor like the timing of specific operations.
A cycle accurate simulator (CAS) of a processor models the processor at a higher level of abstraction than low level simulators. Typically, a CAS of a processor models the performance of a processor, models the timing of various operations within a processor, and is consequently slower than the IAS of the processor, while still being faster than the low level simulators.
Executing operating system boot up programs and executing long-running benchmark or validation programs on such high level simulators is much faster than executing them on low level simulators. For example, in validating the functionality and/or performance of the aforementioned two hundred megahertz processor, a high level simulator, particularly the IAS of a processor, running at a speed of one megahertz would require two hundred minutes, or about 3.3 hours, to run an operating system bootup program, which the processor would require only one minute to execute. However, the high level simulator cannot completely and accurately model the many complexities in a processor because the high level simulator only represents the functions of the processor and not every gate and not every connection of the processor. Therefore, executing operating system boot up programs and executing long-running benchmark or validation programs on a high level simulator, such as the IAS of a processor, neither validate the functionality of the processor nor give a highly accurate prediction of the performance of the processor.
For the foregoing reasons, a system and method that validates the performance and functionality of a processor in a highly accurate, timely, relatively inexpensive, and easy manner would benefit processor design.